8085 Microprocessor : Timing Diagram

( summerized, source:http://www.newagepublishers.com/)

Introduction

Timing diagram is the display of initiation of read/write and transfer of data operations under the control of 3-status signals IO / M , S1, and S0. As the heartbeat is required for the survival of the human being, the CLK is required for the proper operation of different sections of the microprocessors. All actions in the microprocessor is controlled by either leading or trailing edge of the clock.The 3-status signals : IO / M, S1, and S0 are generated at the beginning of each machine cycle. The unique combination of these 3-status signals identify read or write operation and remain valid for the duration of the cycle. Table-5.1(a)shows details of the unique combination of these status signals to identify different machine cycles. Thus, time taken by any μP to execute one instruction is calculated in terms of the clock period.

The instruction cycle consists of two cycle

Fetch Cycle
Execution Cycle

Fetch Cycle: It is the operation of fetching the instruction from the memory into the processor.

Execution Cycle:It is the operation of executing the instruction.

The time taken by the μP in performing the fetch and execute operations are called fetch

and execute cycle. Thus, sum of the fetch and execute cycle is called the instruction cycle as

indicated in Fig. 5.2 (a).

It is well known that an instruction cycle consists of many machine cycles. Each machine cycle consists of many clock periods or cycles, called T-states. The 1st machine cycle (M1) of every instruction cycle is the opcode fetch cycle. In the opcode fetch cycle, the processor comes to know the nature of the instruction to be executed. The processor during (M1 cycle) puts the program counter contents on the address bus and reads the opcode of the instruction through read process. The T1, T2, and T3 clock cycles are used for the basic memory read operation and the T4 clock and beyond are used for its interpretation of the opcode. Based on these interpretations, the µP comes to know the type of additional information/data needed for the execution of the instruction and accordingly proceeds further for 1 or 2-machine cycle of memory read and writes

The Op. code fetch cycle is of fixed duration (normally 4-states), whereas the instruction cycle is of variable duration depending on the length of the instruction. As an example, STA instruction, requires opcode fetch cycle, lower-order address fetch cycle and higher order fetch cycle and then the execute cycle. Thus opcode fetch cycle is of one machine cycle in this example. A particular microprocessor requires a definite time to performing a specific task. This time is called machine cycle. Thus, one machine cycle is required each time the µP access I/O port or memory. A fetch opcode cycle is always 1-machine cycle, whereas, execute cycle may be of one or more machine cycle depending upon the length of the instruction.

Instruction Fetch (FC) ⇒ An instruction of 1 or 2 or 3-bytes is extracted from the memory locations during the fetch and stored in the µP’s instruction register. Instruction Execute (EC) ⇒ The instruction is decoded and translated into specific activities during the execution phase. Thus, in an instruction cycle, instruction fetch, and instruction execute cycles are related as depicted in Fig. 5.2 (a). Every instruction cycle consists of 1, 2, 3, 4 or 5-machine cycles as indicated in Fig. 5.2 (c). One machine cycle is required each time the µP access memory or I/O port. The fetch cycle, in general could be 4 to 6-states whereas the execute cycle could of 3 to 6-states. The 1st machine cycle of any instruction is always the fetch cycle that provides identification of the instruction to be executed.

TIMING DIAGRAM OF OPCODE FETCH

The process of opcode fetch operation requires minimum 4-clock cycles T1, T2, T3, and T4 and is the 1st machine cycle (M1) of every instruction. Example Fetch a byte 41H stored at memory location 2105H. For fetching a byte, the microprocessor must find out the memory location where it is stored. Then provide condition (control) for data flow from memory to the microprocessor. The process of data flow and timing diagram of fetch operation are shown in Figs. 5.3 (a), (b), and (c). The µP fetches opcode of the instruction from the memory as per the sequence below

A low IO/ M means microprocessor wants to communicate with memory.
The µP sends a high on status signal S1 and S0 indicating fetch operation.
The µP sends 16-bit address. AD bus has address in 1st clock of the 1st machine cycle, T1.
AD7 to AD0 address is latched in the external latch when ALE = 1.
AD bus now can carry data
In T2, the RD control signal becomes low to enable the memory for read operation.
The memory places opcode on the AD bus
The data is placed in the data register (DR) and then it is transferred to IR.
During T3 the RD signal becomes high and memory is disabled.
During T4 the opcode is sent for decoding and decoded in T4.
The execution is also completed in T4 if the instruction is single byte.
More machine cycles are essential for 2- or 3-byte instructions. The 1st machine cycle M1 is meant for fetching the opcode. The machine cycles M2 and M3 are required either to read/ write data or address from the memory or I/O devices.

TIMING DIAGRAM OF READ CYCLE

The high order address (A15 ⇔ A8) and low order address (AD7 ⇔ AD0) are asserted on 1st low going transition of the clock pulse. The timing diagram for IO/M read are shown in Fig. 5.3 (e) and ( f ). The A15 ⇔ A8 remains valid in T1, T2, and T3 i.e. duration of the bus cycle, but AD7 ⇔ AD0 remains valid only in T1. Since it has to remain valid for the whole bus cycle, it must be saved for its use in the T2 and T3.

ALE is asserted at the beginning of T1 of each bus cycle and is negated towards the end of T1. ALE is active during T1 only and is used as the clock pulse to latch the address (AD7 ⇔ AD0) during T1. The RD is asserted near the beginning of T2. It ends at the end of T3. As soon as the RD becomes active, it forces the memory or I/O port to assert data. RD becomes inactive towards the end of T3, causing the port or memory to terminate the data.

TIMING DIAGRAM OF WRITE CYCLE

Immediately after the termination of the low order address, at the beginning of the T2, data is asserted on the address/data bus by the processor. WR control is activated near the start of T2 and becomes inactive at the end of T3. The processor maintains valid data until after WR is terminated. This ensures that the memory or port has valid data while WR is active. It is clear from Figs. 5.3 (g) and (h) that for READ bus cycle, the data appears on the bus as a result of activating RD and for the WR bus cycle, the time the valid data is on the bus overlaps the time that the WR is active.

Example:

STA :The STA instruction stands for storing the contents of the accumulator to a memory location whose address is immediately available after the instruction (STA).

Since the STA instruction is meant to store the contents of the accumulator to the memory location, it is a 3-byte instruction. 1st byte is the opcode, the 2nd and 3rd bytes are the address of the memory locations. The storing of the STA instruction in the memory locations is as

Opcode 1st byte
Low address 2nd byte
High address 3rd byte

Three machine cycles are required to fetch this instruction : opcode Fetch transfers the opcode from the memory to the instruction register. The 2-byte address is then transferred, 1-byte at a time, from the memory to the temporary register. This requires two Memory read machine cycles. When the entire instruction is in the microprocessor, it is executed. The execution process transfers data from the microprocessor to the memory. The contents of the accumulator are transferred to memory, whose address was previously transferred to the microprocessor by the preceding 2-Memory Read machine cycles. The address of the memory location to be written is generated as