Delay calculation ( cont.)

Time delay using  a Register Pair

As mentioned in earlier post, we can use register pair to create large delay. We need to consider the thing that we cannot check whether the register pair is zero or not using jump instruction( jz/jnz) . So,We use OR instruction to check whether the register pair is zero or not.

Code for delay using register pair

LXI          D, 16 bit count (10 T states)        

LOOP:   DCX        D                             (6 T states)

MOV     A,E                         (4 T states)

ORA       D                             (4 T states)

JNZ         LOOP                     (10/7 T states)

How this code works?

The instruction LXI D, count : loads DE register pair with specified data.

The instruction DCX D decreases the DE register pair by  one.( the problem is DCX instruction doesn’t change the zero flag, so we cannot use JZ or JNZ instruction. To overcome this problem, we use OR instruction . We do logic OR between D register and E register. If both register contains zero then only zero flag will be set which is the needed condition for us).

The instruction MOV A, E:  to perform logical OR operation between the contends of E and D , one data needs to move to A register. Here ,we are moving contends of E register to Accumulator.

The instruction ORA D : Performs logical OR operation between Accumulator with Register D. This instruction sets the Zero flag only when the contents of D and E are simultaneously zero.

The instruction JNZ  LOOP : checks whether the zero flag is set or not. If the Zero flag is not set ,the flow of program will jump to given label ( LOOP Here) else the flow will jump below jnz loop instruction.

Delay calculation

if the clock frequency of the system f = 2MHZ

clock period (T) = 1/f = 1/2*10 power-6 = 0.5 microsecond

here, we have to calculate three time variable (t0, tL , tLA)

time to execute LXI D, 16 bit count

to           = 10 T

                =10 x 0.5 microsecond

to            = 5 microsecond

Time to execute

 LOOP:  DCX        D                             (6 T states)

MOV     A,E                         (4 T states)

ORA       D                             (4 T states)

JNZ         LOOP                     (10/7 T states)

time delay in loop (tL) = T x loop T states x 16 bit count

here T = 0.5 microsecond

loop T states = 6T +4T+ 4T+ 10T = 24T

  

  tL = 0.5 microsecond x 24 x 16-bit-count

  tL = (12 x 16-bit-count) microsecond

    

The T states for JNZ is 10/7

so we also have to consider the 7T states of JNZ . when the loop executes for specified count times , and at last when the condition is false , the T states it takes will be only 7T so we have to subtract 3T from the tL that we have calculated above.

tLA = 3T

= 3 x 0.5 microsecond

   = 1.5 microsecond

now total time taken tt is given by

  tt= t0 + tL - tLA

   = 5 + (12 x 16-bit-count ) -1.5 microsecond

  tt = 3.5 + 12 x 16-bit-count

now if you need delay for 50 milli second then

  50ms = 3.5 + 12 x 16-bit-count microsecond

 

16-bit-count = (50000-3.5)/12

16-bit-count =4,166 in decimal which is equivalent to 1046 hexadecimal value

the maximum value that can be loaded in register pair is FFFFH (which is equivalent to 65535 decimal value), with this value the maximum delay is

Max delay = 3.5 + 12 x 65535 =786,423.5 microsecond

                                                                  = 786.4235 milli second                                                                   

                                                                  = 0.7864235 second

This is maximum delay at system clock  frequency 2 Mhz. It differs with system clock frequency.

For example if the clock frequency is 1 Mhz( then T=1) then the maximum delay will be calculated as

Total delay = 10T +( 24x65535)T -3T  microsecond

       =10 +( 24x65535) -3  microsecond ( since T=1)

      = 1.572847 second

This is maximum delay at system clock  frequency 1 Mhz.

Time Delay using loop within loop

A multiple loop is used to create a large delay. Here we are using loop within a loop

Code :

 

mvi b, count       7t-states

loop2:   mvi c, ffH             7t-states             

loop1:   dcr c                       4t-states                  loop1

                jnz loop1              10/7 t –states                                    loop2

                dcr b                      4t-states

                jnz loop2              10/7 t -states

 

if the clock frequency of the system f = 2MHZ

clock period (T) = 1/f = 1/2*10 power-6 = 0.5 microsecond

 

for loop1:

total delay( tl1) = 7t+(4t+10t) x 255-3t = 4t + (14t x 255)= 4x0.5 +(14 x 0.5 x 255) = 1787 microsecond

for loop2:

total delay (td) =

= 7t+( tl1 + 4t + 10t) x count  – 3t

                = 4t + ( tl1 + 14t) x count  

                = 4 x 0.5 + ( 1787 + 14 x 0.5) x count

Td           = 2 + 1,794 x count

 Suppose you need to create a delay for 100ms , then

100000 microsecond = 2 + 1,794 x count

Count = (100000-2)/ 1794 = 55.7402 = 56 decimal value = 38 H ( hexadecimal value)

The maximum delay ( at count= ff H)  is 2 + 1794 x 255 = 457,472 microsecond = 457.472 milli second = 0.45 second.

When the system frequency is operating at 2 Mhz.

Question: What will be the maximum delay using two register pairs used in nested loop, if the crystal frequency is 4 MHz?

Let’s have a delay program using two register pairs used in nested loop

 

LXI          B, FFFF H  (10 T states)

//inner loop start

LOOP2:

LXI          D, FFFF H          (10 T states)        

LOOP1:   DCX        D        (6 T states)

MOV     A,E                       (4 T states)

ORA       D                          (4 T states)

JNZ         LOOP1                (10/7 T states)

//inner loop ends

 

 DCX        B         (6 T states)

MOV     A,C                       (4 T states)

ORA       B                          (4 T states)

JNZ         LOOP2                (10/7 T states)

 

Delay calculation

Since given crystal frequency is 4Mhz , them T= 1/f = 1/(4 x 10⁶) second = 0.25x10^-6  second

T = 0.25 micro second

For inner loop

Delay =  10T +( 24 x FFFFh )T -3T  second

          = 10T +( 24 x 65535)T -3T  second ( here FFFFh =  65535 decimal value)

 

Delay = 10T +( 24x65535)T -3T 

            = 7 x (0.25) +(24 x 65535 ) x 0.25  microsecond =  393211.75 Microsecond

            = 0.39321175 second

 

Now total delay calculation ( including inner and outer loop)

= 10T + ( 0.39321175 + 24T) x FFFFh  – 3T   second

= 10T + ( 0.39321175 + 24T) x 65535 – 3T   second   ( here FFFFh =  65535 decimal value)

=7T +( 0.39321175 + 24T) x 65535    second

=(7 x 0.25 x 10^-6) + (0.39321175 + 24 x 0.25 x 10^-6) X 65535   second

= 25769.525248 second

This is maximum delay at system clock  frequency 4 Mhz using two register pairs used in nested loop